1. Introduction
ModelSim is quick and handy VHDL/Verilog simulator. From this document you can find short introduction how to use ModelSim without design manager or other Mentor applications (i.e., as a stand alone tool).
2. Introduction
Before using ModelSim you have to initialize few variables etc. Refer to section Getting Started with ModelSim.
3. Beginners' Guide
Your VHDL code must be compiled into a VHDL library before it can be simulated. Simulator itself can't read VHDL source code, it can only simulate a compiled database (think it as a compiled program).
In the compilation phase all syntactical bugs/typos will be pointed out. After you have succesfully managed to compile the design, actual simulation/debugging of semantical mistakes (= design errors) may begin. (In fact ModelSim may point out some possible design pitfalls already in compilation phase.)
You can manage your VHDL libraries with following shell commands. Study them carefully:
vlib Create a new library
vmap Map physical and logical library
vdir List currently compiled design units
vdel Delete a design unit
vmake Automatically generate Makefile
Compilation and simulation commands:
vcom Compile VHDL source code
vsim Simulate compiled design
4. Exercises and demos
In the following example we will design simple traffic lights control circuit with behavioral vhdl. We will compile and simulate vhdl with ModelSim and study how to create and manage VHDL libraries in practice. Then we will improve the functionality of our traffic lights editing the source code and verifying our changes with second simulation.
First we need a VHDL library where we can compile our source code.
Create two libraries (codelib and traffic_lib)
% vlib codelib
% vlib traffic_lib
As you can see vlib created two directories (codeliband traffic_lib) and one file into each of the directories (_index or _info). That file contains information about compiled VHDL sources and the state of the library (of cource at this moment both of these files are empty). You should never edit these files yourself 'by hand'. Let the ModelSim itself handle its own bookcounting. In order to change the state of the library use only appropriate library commands.
Now we must tell ModelSim where our newly created libraries are located in physical media (= path on the disk we are using).
Map the physical and logical library
% vmap codelib $PWD/codelib
% vmap traffic_lib $PWD/traffic_lib
$PWD here represents full path to the physical library.
vmap writes an initialization file called modelsim.ini into your working directory which contains information about your working environment (like which libraries you are using etc.).
Hint: If you use only vmap without parameters you will get a list of currently mapped libraries, which ModelSim.ini you are currently using and physical location of every library.
Download following vhdl files: (click on right mouse button and choose Save link as)
Compile the source code:
Compile the vhdl package into the traffic_lib:
% vcom package.vhdl -work traffic_lib -source
The following command-line options can be used with vcom:
-work path
Specify library WORK
-nowarn #
Do not flag warnings for the warning number specified.
-line #
Specify starting line number
-source
Print the VHDL source line with error messages
-just e,a,p,b,c
Compiles only the specified units (entities, architectures, package headers, package bodies, configurations)
-skip e,a,p,b,c
Compiles everything except the specified units (entities, architectures, package headers, package bodies, configurations)
Note that vcom always compiles sources to the library work. The only way to compile designs other libraries than work is to rename the work. This can be done with -work switch in vcom like we did in the package's case or remapping the work into another library with vmap.
% vmap destination_library work (This command is not ment to be performed)
Now work points to the destination_library and -work -switch may be omitted. Remember that you can always check your current mapping just typing vmap without any parameters.
Map the work to codelib and compile the architecture and entity into it.
Map the work into codelib:
% vmap work $PWD/codelib
Try now vmap...
% vmap
Reading /home/user/.ModelSim.ini
"work" maps to directory /home/user/codelib/.
"codelib" maps to directory /home/user/codelib/.
...
Verify that you mappings are something like above. After that you can compile the source code into codelib...
% vcom top_level_entity.vhdl -source
% vcom behavioral.vhdl -source
Soon you will notice that VHDL design cycle is something like edit-compile-simulate-edit-compile... It is quite annoying always write same compilation commands every design cycle. One can always write a shell script, but if your design is large enough compilation times may be quite long. Those who are familiar with make knows that it is answer to all these problems. Fortunately in ModelSim there is a command which automatically generates a Makefile for your design hierarchy.
Generate a Makefile from the codelib's sources:
% vmake codelib > Makefile
In order to keep your library up-to-date, you have to only give a command make. Make knows which files have been edited and automatically compiles only needed designs.
More information about make and Makefile from UNIX manuals (% man make) See also: man touch.
Now you are ready to simulate out traffic lights!
% vsim &
First ModelSim prompts you to choose the entity-architecture pair you want to simulate. Select the traffic_lights entity and just press Load. Soon a window (like following picture) should open.
Then expand the library codelib on library list window. (After that the view is like below)
Then load the traffic_lights. (double click the text traffic_lights or first select it by clicking it once and then take from menu Simulate - Simulate)
There are two ways to give commands to ModelSim. You can either choose commands with mouse from simulator's GUI or write them directly to the command line. Try for example writing:
VSIM> view signals
Or try to choose from ModelSim (ModelSim : View - Signals).
You can also write scripts and then execute them by choosing (ModelSim : Macro - Execute Macro...)
Simulation
View the wave -window by choosing (ModelSim : View - Signals) and (Signals : Add - Wave - Signals in Region) or by writing to the command line:
VSIM> add wave *
You can force signals from (Signals : Edit - Force...) or clock signal (Signals: Edit - Clock) or by writing commands to the command line:
VSIM> force -deposit /clk 1 5 -repeat 20
VSIM> force -deposit /clk 0 10 -repeat 10
VSIM> force -deposit /reset 0 0
VSIM> force -deposit /reset 1 15
Now press run button couple of times or (Modelsim : Simulate - Run):
You should see simulation results in the wave-window.
Configuring environment
You can move signals up and down in the Wave-window with the mouse. You can add signals from different entities to the same wave window by first pointing right entity from structure windown, choosing signal(s) from signal window and then giving command (Signals : Add - Wave - Selected signals). Of cource, that is not possible in our trafficlight example (we only have one entity).
Saving the configuration
After your simulation environment is ready, you can save it in the script file as a configuration for future use by choosing (Wave : File - Save Format...). Saved configuration can be read by choosing (ModelSim : File - Load Format...) and choosing the file you have saved.
Debugging VHDL with trace
You can trace your vhdl source code: First view Source (ModelSim : View - Source) or VSIM> view source and then press (ModelSim : Step) or (ModelSim : Step Over) buttons.
Our traffic lights has no output for actual light bulbs. It is only a state machine at the moment. That is why we are now going to improve our design by adding output signals wires to every bulb (reg, yellow and green).
Choose your favorite editor (like emacs) and edit the top level entity (top_level_entity.vhdl):
ENTITY traffic_lights IS
PORT ( clk,
reset : IN std_logic;
red_light,
orange_light,
green_light : OUT std_logic);
END traffic_lights;
And then edit the architecture (behavioral.vhdl):
CASE current_state IS
WHEN red =>
IF (count = 20) THEN
next_state <= orange;
count := 0;
red_light <= '1';
orange_light <= '0';
green_light <= '0';
END IF;
WHEN orange =>
IF (count = 5) THEN
next_state <= green;
count := 0;
red_light <= '1';
orange_light <= '1';
green_light <= '0';
END IF;
WHEN green =>
IF (count = 20) THEN
next_state <= red;
count := 0;
red_light <= '0';
orange_light <= '0';
green_light <= '1';
END IF;
WHEN OTHERS =>
next_state <= current_state;
END CASE;
Now we have to recompile edited VHDL sources before we can simulate our enhanced design. Make will do that for us automatically.
Save changes and goto to the shell prompt and give command:
% make
(Note that if you took a new shell you must first execute your Mentor initialization script unless you have edited your .cshrc file to include the source commands and goto the directory where your libraries, codes and Makefile are.)
After compilation you must load new design to the simulator. If you did not Quit the simulator just give the command:
VSIM> restart -force
Otherwise you must start the simulator again:
% vsim &
Now you can simulate and verify our new design. Try to view all signals (including those we just added).
5. More Information
For more information refer to the OnLine Manuals. |
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